An effectual elucidation of task scheduling and memory partitioning for MPSoC

Abstract

In upcoming technologies multiprocessors are used for the efficient performance improvement. The multi processor system on chip is the complex embedded system used in multimedia applications for the resource utilization and simultaneous accessing. The MPSoC is the processor which uses the n number of resources such as peripherals, devices and processing elements for the improvisation of speed and performance which in turn reduces the execution time and energy dissipation. In general we use the offchip memory which has the cache in order to reduce the time of data fetch. In off chip memory access they use the decoupled approach where the partitioning and allocation of tasks to processor are done separately. Scratch Pad Memory is the fast on-chip memory which is the part of integrated chip memory (RAM). The SPM is the on-chip memory which can be used for the integration approach of task scheduling and memory partitioning. The integrated approach uses heuristics algorithm which increases the performance but when data needed is not available it leads to cache conflict. Thus the cache conflict is also been resolved by the use of segmented LRU algorithm. By the use of these two algorithms the execution cycle time is been reduced which can be evaluated using various benchmarks.