Linlin Zhang, V. Fresse, Mohammed A. S. Khalid, D. Houzet, M. Ahmadi, A. Legrand, Viktor Fischer
{"title":"Evaluation of NoC dedicated to multispectral image data communication","authors":"Linlin Zhang, V. Fresse, Mohammed A. S. Khalid, D. Houzet, M. Ahmadi, A. Legrand, Viktor Fischer","doi":"10.1109/ISSCS.2009.5206177","DOIUrl":null,"url":null,"abstract":"An efficient Network on Chip (NoC) is proposed for the data communication of multispectral image analysis algorithms on an adaptive architecture. A Butterfly Fat Tree (BFT) topology is used in this NoC on FPGA. Since there are large amount of data with different sizes in the NoC, Virtual Channels (VC) with flit packet-switching is chosen. Two versions of the NoC are presented in this paper. The results of the implementations on Altera StratixII and Xilinx Virtex4 are analyzed. It is shown that the required resources are similar but the frequency on Xilinx is much faster than on Altera.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on Signals, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2009.5206177","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An efficient Network on Chip (NoC) is proposed for the data communication of multispectral image analysis algorithms on an adaptive architecture. A Butterfly Fat Tree (BFT) topology is used in this NoC on FPGA. Since there are large amount of data with different sizes in the NoC, Virtual Channels (VC) with flit packet-switching is chosen. Two versions of the NoC are presented in this paper. The results of the implementations on Altera StratixII and Xilinx Virtex4 are analyzed. It is shown that the required resources are similar but the frequency on Xilinx is much faster than on Altera.