An energy-efficient power-gating adiabatic circuits using transmission gate switches

D. Zhou, Jianping Hu, Huiying Dong
{"title":"An energy-efficient power-gating adiabatic circuits using transmission gate switches","authors":"D. Zhou, Jianping Hu, Huiying Dong","doi":"10.1109/ICASIC.2007.4415588","DOIUrl":null,"url":null,"abstract":"This paper presents a new power-gating technique for adiabatic circuits to reduce energy loss during idle state. The power-gating switches based on DTGAL (dual transmission gate adiabatic logic) circuits are used to detach adiabatic logic blocks from power-clocks. The energy overhead optimization for the proposed power-gating scheme is investigated. The 8-bit full adders based on DTGAL circuits are verified using the proposed power-gating technique. All circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss is reduced greatly by shutting down idle adiabatic logic blocks.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

This paper presents a new power-gating technique for adiabatic circuits to reduce energy loss during idle state. The power-gating switches based on DTGAL (dual transmission gate adiabatic logic) circuits are used to detach adiabatic logic blocks from power-clocks. The energy overhead optimization for the proposed power-gating scheme is investigated. The 8-bit full adders based on DTGAL circuits are verified using the proposed power-gating technique. All circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss is reduced greatly by shutting down idle adiabatic logic blocks.
一种采用传输门开关的节能电源门控绝热电路
本文提出了一种用于绝热电路的新型功率门控技术,以减少电路在空闲状态下的能量损失。采用基于DTGAL(双传输门绝热逻辑)电路的功率门开关,将绝热逻辑模块与功率时钟分离。研究了所提出的功率门控方案的能量开销优化问题。采用功率门控技术对基于DTGAL电路的8位全加法器进行了验证。所有电路均采用台积电0.18 mum CMOS技术的BSIM3V3模型进行验证。通过关闭空闲的绝热逻辑块,能量损失大大减少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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