Tetsuro Honmura, Yuki Kondo, Tetsuya Yamada, M. Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, H. Nishi, Mikiko Sato, M. Namiki
{"title":"Hardware support for resource partitioning in real-time embedded systems","authors":"Tetsuro Honmura, Yuki Kondo, Tetsuya Yamada, M. Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, H. Nishi, Mikiko Sato, M. Namiki","doi":"10.1109/CoolChips.2013.6547922","DOIUrl":null,"url":null,"abstract":"Today's embedded systems require multiple functions such as real-time control and information technology and integrating these functions on a multi-core processor is one effective solution. However, this increases overhead as it is necessary to partition resources in this approach to protect them. We developed hardware support called ExVisor/XVS to reduce the overhead of partitioning resources to achieve real-time characteristics. This features a physical address management module (PAM) that uses direct address translation by using a single level page table based on an embedded system's memory usage. We evaluated the overhead in a virtual machine's (VM) resource access through register transfer level (RTL) simulation and implementation on a field-programmable gate array (FPGA), and it was only less than 5.6% compared with the resource access time by a single core processor.","PeriodicalId":340576,"journal":{"name":"2013 IEEE COOL Chips XVI","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE COOL Chips XVI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CoolChips.2013.6547922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Today's embedded systems require multiple functions such as real-time control and information technology and integrating these functions on a multi-core processor is one effective solution. However, this increases overhead as it is necessary to partition resources in this approach to protect them. We developed hardware support called ExVisor/XVS to reduce the overhead of partitioning resources to achieve real-time characteristics. This features a physical address management module (PAM) that uses direct address translation by using a single level page table based on an embedded system's memory usage. We evaluated the overhead in a virtual machine's (VM) resource access through register transfer level (RTL) simulation and implementation on a field-programmable gate array (FPGA), and it was only less than 5.6% compared with the resource access time by a single core processor.