FPGA implementation of acoustic echo cancelling

Abstract

This paper presents the details of the realisation of a previously proposed LMS-Newton algorithm using field programmable gate array (FPGA). On one Xilinx XC4062XL chip, we designed a 578-tap adaptive filter, which operates at a sampling rate of up to 29.4 kHz. We discuss the word-length requirement of various modules in the design. An interesting finding which has been ignored in most earlier publications is that although a relatively long word-length should be used for the filter tap-weights to prevent the stalling phenomenon, the actual tap-weight bits which should be used to calculate the filter output can be many bits less. The proposed design is cascadable, meaning that by cascading a few chips, adaptive filters with lengths at a multiple of 578 could be implemented.