Slew-aware fast clock tree synthesis with buffer sizing

Abstract

Clock tree synthesis (CTS) is a critical part on the total performance of chip. Buffer insertion is required in clock tree to prevent signal degradation and satisfy slew constraints. Also, buffer sizing minimizes power and skew in clock tree network. In this paper, we proposed slew-aware fast buffer insertion/sizing methodology in CTS based on DME to meet the skew constraints. The experiment results show the proposed sizing method reduce about 13.47% power consumption and 49.03% runtime compared to LP-based method.