Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs

Abstract

Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3D ICs. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for known-good-die (KGD) test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond TSV and pre-bond scan test can be performed. The drawback of die wrappers is that two clocked stages are added to each path that crosses a die boundary. In this paper, a bypass mode is added to GSFs to avoid the extra clock stages and retiming is used to recover the additional delay added to through-silicon-via (TSV) paths by design-for-test (DfT) insertion. The proposed method is evaluated through simulations using a logic-on-logic 3D benchmark. Results show that in most cases, retiming at both the die-level and stack-level is sufficient for recovering the delay added by wrapper boundary cells. Stuck-at ATPG is performed to demonstrate that wrapper insertion and retiming have little impact on pattern count. The area overhead due to wrapper insertion is shown to increase as a circuit is partitioned across an increasing number of stack layers, but the area overhead can be reduced using retiming.