An Efficient 32-bit Ladner Fischer Adder derived using Han-Carlson

Abstract

Parallel-prefix adders propose an extremely efficient solution to the binary addition problem. Adders are building block in digital circuit that performs addition of two numbers. In VLSI design, a parallel- prefix adder is a kind of adder that performs efficient addition by using the prefix operation. In this Research, a 32 bit Ladner-Fischer parallel prefix adder, a category of a parallel prefix adder that executes addition operations in parallel. Nevertheless, through the use of a black cell, the performance of the Ladner Fischer adder took a large amount of space. As a result, the gray cell has been used instead of the black cell, resulting in the Ladner-Fischer Adder Efficiency. Earlier Ripple carry adder waited for previous bit for every bit addition which was overcome by Ladner Fischer adder. The proposed system introduced D register stage which increases the performance with reduce in delay to 7.165ns and LUT count is 82.