F. Vargas, L. Picolli, Antonio A. de Alecrim, M. Moraes, Marcio Gama
{"title":"Summarizing a time-sensitive control-flow checking monitoring for multitask systems-on-chip","authors":"F. Vargas, L. Picolli, Antonio A. de Alecrim, M. Moraes, Marcio Gama","doi":"10.1109/FPT.2006.270320","DOIUrl":null,"url":null,"abstract":"This paper summarizes a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected CPU instruction sequence and that as consequence, change also (by increasing or reducing) the expected CPU time allocated for the execution of the monitored task. The underlined advantage of this approach is the ability of detecting faults in multitask systems-on-chips (SoCs) running under the control of a real-time (preemptive) operating system. In this multi-task scenario, the I-IP can perform fault detection in a time-shared basis. Practical experiments have been carried out and results are discussed","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on Field Programmable Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPT.2006.270320","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper summarizes a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected CPU instruction sequence and that as consequence, change also (by increasing or reducing) the expected CPU time allocated for the execution of the monitored task. The underlined advantage of this approach is the ability of detecting faults in multitask systems-on-chips (SoCs) running under the control of a real-time (preemptive) operating system. In this multi-task scenario, the I-IP can perform fault detection in a time-shared basis. Practical experiments have been carried out and results are discussed