{"title":"A 227.5GHz InP HBT SSPA MMIC with 101mW Pout at 14.0dB Compressed Gain and 4.04% PAE","authors":"Z. Griffith, M. Urteaga, P. Rowell, R. Pierson","doi":"10.1109/CSICS.2013.6659190","DOIUrl":null,"url":null,"abstract":"A 214-230GHz solid-state power amplifier (SSPA) MMIC is presented, where at 227.5GHz it simultaneously demonstrates 101mW P,out at 14.0dB compressed gain (4.0mW P,in), with 4.04% PAE - these record SSPA MMIC values represent increases to state-of-the-art by 12% for P,out and 2.3× for PAE at these frequencies in an HBT technology. The maximum compressed Pout is 103mW at 13.1dB gain (5.0mW P,in) and 4.08% PAE. This 2-stage amplifier has 19-21dB S21 gain from 214-235GHz, with 3-dB S21 bandwidth of 240GHz. P,DC is 2.40W. Amplifier cells were fabricated from a 250nm InP HBT technology, jointly with a substrate-shielded, thin-film microstrip wiring environment using BCB. The 80-103mW P,out (214-230GHz) is achieved by 8-way (4-way × 2-way) combining eight cascode cells. Due to the gain of the cascode cell being 10-11dB, a four cascode cell combined predriver could be used to drive the amplifier output stage into saturation - this reduces to SSPA PDC and improves PAE. Across the SSPA bandwidth, the 2:1 and 4:1 power dividers/combiners exhibit only 0.4dB and 0.5dB loss respectively.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2013.6659190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 214-230GHz solid-state power amplifier (SSPA) MMIC is presented, where at 227.5GHz it simultaneously demonstrates 101mW P,out at 14.0dB compressed gain (4.0mW P,in), with 4.04% PAE - these record SSPA MMIC values represent increases to state-of-the-art by 12% for P,out and 2.3× for PAE at these frequencies in an HBT technology. The maximum compressed Pout is 103mW at 13.1dB gain (5.0mW P,in) and 4.08% PAE. This 2-stage amplifier has 19-21dB S21 gain from 214-235GHz, with 3-dB S21 bandwidth of 240GHz. P,DC is 2.40W. Amplifier cells were fabricated from a 250nm InP HBT technology, jointly with a substrate-shielded, thin-film microstrip wiring environment using BCB. The 80-103mW P,out (214-230GHz) is achieved by 8-way (4-way × 2-way) combining eight cascode cells. Due to the gain of the cascode cell being 10-11dB, a four cascode cell combined predriver could be used to drive the amplifier output stage into saturation - this reduces to SSPA PDC and improves PAE. Across the SSPA bandwidth, the 2:1 and 4:1 power dividers/combiners exhibit only 0.4dB and 0.5dB loss respectively.