High voltage trench drain LDMOS-FET using SOI wafer

Abstract

Silicon direct bonding and deep trench techniques are a good combination for high density and high voltage ICs such as display drivers. High voltage devices in these ICs are perfectly isolated by thick SOI oxide and isolation trenches. The SOI oxide thickness increases the blocking voltage of full depletion devices. On the other hand, it increases the warpage of SOI wafers and makes troubles in handling them. The new trench drain structure solves these problems and provides high voltage, low ON resistance LDMOS-FET. Its drain-source blocking voltage is 290 V, and the ON resistance is 0.37 /spl Omega/cm/sup 2/ including the isolation area.