1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance

Abstract

Achieving higher effective resolution bandwidth (ERBW) beyond Nyquist frequency is a key design requirement for the slice ADC design in a time-interleaved ADC (TIADC). While SAR ADC is a popular choice for a low-power ADC in advanced CMOS processes, the input capacitance $(\mathrm{C}_{in})$ presented by the front-end capacitive DAC (CDAC) to the ADC input limits achievable signal bandwidth. In contrast, pipelined SAR ADCs has more freedom in choosing Cin because the resolution of the 1st stage CDAC can be much lower than the total resolution. Therefore, it is possible to reduce Cin to the thermal noise limit without being limited by the minimum unit capacitance. The downside of the pipelined SAR ADCs is the necessity of a residue amplifier, which often dominates the total power consumption. One can consider using a dynamic amplifier (DA) as a residue amplifier because achieving both high speed and low power is possible when the desired gain is modest [1–2]. Being an open-loop and fully-dynamic, however, the DA suffers from the gain inaccuracy and is vulnerable to the kickback noise. Furthermore, the gain varies significantly over process and temperature. [3] and [4] attempt to solve this issue by temperature-tracking bias but such compensation method requires off-chip and temperature-dependent voltage or resistor to tune the process uncertainty.