Double Mold Fan-Out Wafer Level Packaging for AiP Applications

Abstract

Double molding fan-out wafer level packaging process integration flow was introduced in this paper to achieve miniature scale Antenna-in-package AiP at low transition loss with long distance communication and beam steering capabilities. The size of this package as 12mm × 12mm × 0.40mm. The main components of this package are three redistribution layers (RDL), two mold-compound layers and a through mold via (TMV) structure at 100um depth. A bare silicon chip at 4mm × 4mm was embedded into mold compound layers, with copper metal and polyimide dielectric RDL layers built to interconnect the PCB and the opposite metal ground via Metal TMV structure. Copper antenna was fabricated on top of thick, second-molded-compound layer via IME technology on double molding FOWLP process architectures. This paper demonstrated a double molding fan-out approach to build RDL layers on first-mold reconfigured silicon surfaces; and second mold as the objectives of filling up TMV structures and dielectric interlayer between RF metal and antenna metal layers. The major process challenges and the respective solutions were discussed. The development of critical process parameters was identified to ensure good process specifications and uniformity.