Trading off area, yield and performance via hybrid redundancy in multi-core architectures

Abstract

Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core level of granularity provides great benefits in yield improvement, but requires additional steering logic and wiring that has a detrimental impact on area and performance. At the other end of the spectrum, coarse-grained core level redundancy can enable spare sharing, but it is only beneficial in highly-parallel GPU architectures. To this end, we will 1) introduce a hybrid spare sharing redundancy insertion scheme that combines the advantages of the above two approaches, while carefully leveraging the associated area and performance overheads, 2) present an extensively verified, systematic scalable model to evaluate the quality of the final design in terms of projected revenue per wafer, and 3) introduce a maximization algorithm to determine the near optimal redundancy configurations during the design stage. Experimental results show that our new design methodology provides more than 15% improvement in revenue per wafer, compared to using existing redundancy insertion techniques.