The confluence of manufacturing test and design validation

Abstract

The noise-, process-, thermaland power-induced delay variations make circuit delays much less predictable. At the same time, due to small and subtle defects, devices are more likely to marginally violate performance specifications under scaled technologies. Like the signal lines, clock lines are also becoming more susceptible to variations and defects. For timing verification, such trends invalidate traditional, static (i.e. vector-less) timing verification paradigms and create a demand for dynamic solutions that would require carefully crafted test vectors for accurate timing simulation. For delay testing, we need test vectors that can exercise various worst-case timing scenarios to screen out devices with parametric variations and small timing defects. To reduce the overall costs and effort involved in design and test, we need to develop models, tools, and methodologies that can generate high quality, cost-effective test vectors that serve both applications [1].