Jong-Heon Yang, Jihun Oh, W. Cho, C. Ahn, K. Im, I. Baek, J. Park, Seongjae Lee
{"title":"Impact of reducing RTA temperature on sub-10nm ultra-thin body SOI","authors":"Jong-Heon Yang, Jihun Oh, W. Cho, C. Ahn, K. Im, I. Baek, J. Park, Seongjae Lee","doi":"10.1109/DRC.2004.1367765","DOIUrl":null,"url":null,"abstract":"In this work, we fabricated sub-10 nm UTB SOI and investigated its properties by using plasma doping (PLAD) and rapid thermal annealing (RTA). It is shown, for the first time, that electrical properties and device scalability of the sub-10 nm thin body were improved with reduced RTA temperature. In scaling down, SOI thickness decreases, but also RTA temperature scaling should be considered. RTA temperature is directly connected to the suppression of the short-channel effect and also it gives more chance for device scalability, especially for sub-20 nm SOI devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2004.1367765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, we fabricated sub-10 nm UTB SOI and investigated its properties by using plasma doping (PLAD) and rapid thermal annealing (RTA). It is shown, for the first time, that electrical properties and device scalability of the sub-10 nm thin body were improved with reduced RTA temperature. In scaling down, SOI thickness decreases, but also RTA temperature scaling should be considered. RTA temperature is directly connected to the suppression of the short-channel effect and also it gives more chance for device scalability, especially for sub-20 nm SOI devices.