Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators

Abstract

Video coding requires a massive computational effort leading to large power dissipation and energy consumption. Thus, energy efficiency becomes a significant concern especially under limited energy resources such as in mobile devices. Approximate computing is a promising technique to improve energy efficiency. Therefore, this work presents a new approximate subtractor operator to be used in video coding hardware accelerators. The proposed subtractor reduces power of a Sum of Absolute Differences (SAD) hardware accelerator on approximately 10.39% (on average of different videos) when compared to the use of the subtractor from the synthesis tool. It also presents a power reduction of 18.13% when compared to state-of-the-art approximate adder.