An efficient postprocessor architecture for channel mismatch correction of time interleaved ADCs

Abstract

A pipelined post-processor architecture is proposed in this paper for digital background calibration of time interleaved ADCs. An adaptive filter technique is used for correction of offset and gain mismatches between ADC channels. Only one calibration unit is used for calibrating all ADC channels and increasing in the number of parallel channels in the time interleaved ADC does not considerably affect the required hardware for proposed postprocessor. FPGA synthesis of 10-bit 4-channel processor shows %55 reduction in hardware usage and %25 in power consumption over conventional architecture.