Thermal Data Reduction for Heatsink to Rack Interfaces

Abstract

Component densities and high power dissipations have driven conduction cooled communications enclosures near their practical limits. The thermal resistance at the electronics heatsink to chassis interface acts as a major thermal choke point. Better characterizing the heatsink to chassis thermal interface will allow less conservative designs and increased performance. Extensive testing of the thermal resistance at the heatsink and chassis rail interface has been explored at Harris Corporation. The testing and data reduction focused on a method to accurately model the thermal interface. The resulting test method and data reduction technique served to more accurately characterize the module retainer to chassis interface as a parallel thermal resistance path.