Retiming and clock scheduling to minimize simultaneous switching

Abstract

Today's densely packed deep sub micron (DSM) circuits operate at high frequencies, and draw large amounts of instantaneous currents. The simultaneous switching noise thus induced in the power and ground networks, reduces the circuit noise margins. This work presents a method to minimize the maximum simultaneous switching currents in sequential circuits by the seamless integration of the well known techniques of retiming and clock scheduling. We adopt a gradual relaxation based approach to find an efficient solution to our formulation. Experiments with MCNC benchmark circuits in the 0.18 micron technology show that, on average, our method reduces the maximum simultaneous switching current by 18% compared to unoptimized circuits designed using commercial tools. This improvement was obtained with no decrease in operating frequencies. With a reduction of 17% in power dissipation, on average, our method seems encouraging.