Interconnection and Packaging of Solid State Circuits

Abstract

This paper reviews the growing interaction between the technologies employed to interconnect and package solid state circuits, the circuit design process and the performance of such circuits in a system or sub-system. The nature of this interaction is discussed at all levels of interconnection and packaging, and examples of new developments are cited which present exciting new opportunities to the circuit designer. Particular attention is given to the emerging Multichip Module Packaging concept, which offers a similar level of circuit complexity and integration to Wafer Scale Integration.