Tiger: a timing-driven gate array and standard cell layout system

Abstract

In this paper, we present Tiger, a fast timing-driven layout system for gate array and standard cell design. It can complete whole layout process from placement to detailed routing. The timing issue is directly formulated and considered at every important stage of Tiger based on RC timing model. Several novel and efficient layout algorithms are used in Tiger. Experiments show that Tiger is much faster than TimberWolf 6.0. It guarantees the chip performance while achieving comparable chip area with TimberWolf.