Managing induced warpage of 3D-ICs packaging using multi-layered molding materials

Abstract

Reduced the wafer thickness has high density arrays of through silicon via (TSV). It has significantly required in the assembly technology of three-dimensional integrated circuits (3D-ICs) packages. Find a good approach during the processes. It can decrease the damage risk for stacked chips in chip thinning processes and to enhance the micro-bumps (p-bump) mechanical reliability in this study. A chip-to-wafer (C2W) module filled with a suitable filling the gap at the bottom to a combination of stacked chips and use initialization between the molding material is considered. Compared with traditional technology and methods, significant change in the manufacturing process C2W procedure is filled into the bottom during filling, in order to achieve a pre-lead type material after the step of thinning the chip. The main advantage of the above embodiment is to reduce the thickness of the thinned mechanical load applied to the adjacent molded material, while a highly reduced thickness of the stacked chips to 30 micrometers, the back support is trying to achieve stacked silicon chips. By using the suggested method another advantage is the productivity potential because subsequent packaging process can be greatly simplified.