H. Kuriyama, T. Okada, M. Ashida, O. Sakamoto, K. Yuzuriha, K. Tsutsumi, T. Nishimura, K. Anami, Y. Kohno, H. Miyoshi
{"title":"An asymmetric memory cell using a C-TFT for ULSI SRAMs","authors":"H. Kuriyama, T. Okada, M. Ashida, O. Sakamoto, K. Yuzuriha, K. Tsutsumi, T. Nishimura, K. Anami, Y. Kohno, H. Miyoshi","doi":"10.1109/VLSIT.1992.200635","DOIUrl":null,"url":null,"abstract":"A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cell's size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200635","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cell's size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<>