{"title":"Dynamic reconfigurable multicast interconnections by using radix-4 multistage networks in FPGA","authors":"R. Ferreira, J. Vendramini, Mauro Nacif","doi":"10.1109/INDIN.2011.6034997","DOIUrl":null,"url":null,"abstract":"To fully realize the benefits of rapid reconfiguration of embedded system, we often need a flexible interconnection system. This work proposes a low cost reconfigurable interconnection based on multistage interconnection networks (MINs) for FPGA systems. We show how radix 4 MINs can be efficiently implemented on top of 6 input LUTs. We also show that two parallel blocking MINs could behave as a non-blocking network even in presence of multicast connections. We further show how to route by using software or hardware-assistant approach. The hardware version has a low cost and a high performance. Consequently, route time can be reduced to few clock cycles. We further outline how a global interconnection based on MIN could be used for parallel datapath reconfigurable architectures.","PeriodicalId":378407,"journal":{"name":"2011 9th IEEE International Conference on Industrial Informatics","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 9th IEEE International Conference on Industrial Informatics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INDIN.2011.6034997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
To fully realize the benefits of rapid reconfiguration of embedded system, we often need a flexible interconnection system. This work proposes a low cost reconfigurable interconnection based on multistage interconnection networks (MINs) for FPGA systems. We show how radix 4 MINs can be efficiently implemented on top of 6 input LUTs. We also show that two parallel blocking MINs could behave as a non-blocking network even in presence of multicast connections. We further show how to route by using software or hardware-assistant approach. The hardware version has a low cost and a high performance. Consequently, route time can be reduced to few clock cycles. We further outline how a global interconnection based on MIN could be used for parallel datapath reconfigurable architectures.