Dynamic reconfigurable multicast interconnections by using radix-4 multistage networks in FPGA

R. Ferreira, J. Vendramini, Mauro Nacif
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引用次数: 10

Abstract

To fully realize the benefits of rapid reconfiguration of embedded system, we often need a flexible interconnection system. This work proposes a low cost reconfigurable interconnection based on multistage interconnection networks (MINs) for FPGA systems. We show how radix 4 MINs can be efficiently implemented on top of 6 input LUTs. We also show that two parallel blocking MINs could behave as a non-blocking network even in presence of multicast connections. We further show how to route by using software or hardware-assistant approach. The hardware version has a low cost and a high performance. Consequently, route time can be reduced to few clock cycles. We further outline how a global interconnection based on MIN could be used for parallel datapath reconfigurable architectures.
基于FPGA的基数4多级网络动态可重构组播互连
为了充分实现嵌入式系统快速重构的优势,我们往往需要一个灵活的互联系统。本文提出了一种基于多级互连网络(MINs)的低成本可重构FPGA互连系统。我们展示了如何在6个输入lut之上有效地实现基数4分钟。我们还表明,即使存在多播连接,两个并行阻塞min也可以表现为非阻塞网络。我们进一步展示了如何使用软件或硬件辅助方法进行路由。硬件版本成本低,性能高。因此,路由时间可以减少到几个时钟周期。我们进一步概述了如何将基于MIN的全局互连用于并行数据路径可重构架构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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