A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch

Abstract

A new multiply-by-two gain-stage (MBT-GS)(/spl times/2) is presented in which the gain-sensitivity to the capacitors' mismatches is suppressed. Using one operational amplifier (op-amp) in three phases, a gain of two, which is not highly influenced by the mismatches between the capacitors, is achieved. An analytical study of the architecture is presented followed by some Monte-Carlo simulations using a generic 0.6 /spl mu/m CMOS technology in HSPICE. Simulations clearly show the reduction of the matching-requirements in the new architecture.