Input reordering for power and delay optimization

Abstract

It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate; this has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which drives the reordered gate. It is because the input capacitance depends on signal values of other inputs. We propose a reordering algorithm considering the power dissipation in the driving gate, the reordered gate and the gates driven by the reordered gate. Experimental results using 21 benchmark circuits show that our method reduces the power dissipation in all the circuits by 3.6% on average. There is a possibility that power dissipation is reduced by 17.2% maximum. In the case of delay and power optimization, our method reduces delay by 7.0% and power dissipation by 3.1% on average.