A VLSI asynchronous cellular architecture for neural computing: functional definition and performance evaluation

B. Faure, G. Mazaré
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引用次数: 2

Abstract

Neural networks have two interesting features: robustness and fault tolerance on the one hand, massive parallelism on the other hand. The best way to keep those features and take into account the underlying massive parallelism is to map the neural network over a massively parallel architecture. However, a communication problem remains since the neurons are highly interconnected. A communication system, based on message transfers and without need for allocating a physical link for each connection, seems to be a solution for any parallel machine but is very hard to implement efficiently on hypercubes. We propose a dedicated VLSI architecture based on a two-dimensional array of asynchronous cells, each of which processing the simple algorithms of a neuron : both the back-propagation recall and learning schemes and being connected to its four immediate neighbors through eight unidirectional buffers, one for each way of the four directions. The main feature of this architecture is its hardware-based array-wide message transmission mechanism allowing a particular cell to communicate with potentially any other. A message is passed from a cell to one of its neighbors until it reaches its destination, its path being set dynamically in each passed-through cell. This non local communication system allows to process efficiently a class of distributed algorithms leading to a disorganized parallelism. This paper present the VLSI implementation of this architecture, shows how it can process feed-forward neural networks and discuss its performances. Our implementation of the back-propagation algorithm is at least more than 4 times faster at evaluating the NETtalk text-to-speech network than the Warp, a 20 processor systolic array, which ought to be the fastest back-propagation simulator reported in the literature. Our results indicate that two-dimensional arrays can be good candidates for neural processing, providing they can handle high communication rates.
用于神经计算的VLSI异步细胞架构:功能定义和性能评估
神经网络有两个有趣的特点:一方面是鲁棒性和容错性,另一方面是大规模并行性。保留这些特征并考虑潜在的大规模并行性的最佳方法是将神经网络映射到大规模并行架构上。然而,由于神经元高度互连,通信问题仍然存在。基于消息传输且不需要为每个连接分配物理链路的通信系统似乎是任何并行机器的解决方案,但很难在超多维数据集上有效实现。我们提出了一种基于二维异步单元阵列的专用VLSI架构,每个单元处理神经元的简单算法:反向传播召回和学习方案,并通过八个单向缓冲区连接到它的四个近邻,四个方向的每个方向一个。该体系结构的主要特点是其基于硬件的阵列级消息传输机制,允许特定单元与任何其他单元进行通信。消息从一个单元传递到它的一个邻居,直到它到达目的地,它的路径在每个传递单元中被动态设置。这种非局部通信系统允许有效地处理一类分布式算法,从而导致无组织并行。本文给出了该体系结构的VLSI实现,展示了它如何处理前馈神经网络,并讨论了其性能。我们实现的反向传播算法在评估NETtalk文本到语音网络时至少比Warp快4倍以上,Warp是一个20处理器的收缩阵列,应该是文献中报道的最快的反向传播模拟器。我们的研究结果表明,二维阵列可以很好地用于神经处理,只要它们能够处理高通信速率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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