A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic

Abstract

Low power and high-speed carry look-ahead adder (CLA) is one of the most demanded digital computation units. This paper demonstrates a CLA based on single-phase ANT logic to achieve low power and high speed. It is featured with load capacitance reduction and no internal loop to enhance the speed and reduce switching activity at the same time. The proposed design is proved to work at the clock frequency of 20 GHz with a load of 60 pF implemented using 40 nm CMOS technology by post-layout simulations, where the power dissipation is observed with a normalized 0.071 mW and the normalized PDP is 0.08 pJ.