Design of High Speed, Low Power 16x16 Vedic Multiplier With Adiabatic Logic

Abstract

Multiplication is the major process in all the arithmetic applications. Processors make use of adders and multipliers for all the arithmetic applications. The proposed work presents the efficient usage of Vedic multiplier than the conventional multiplier. The objective is to achieve low power consumptions and reduced propagation delay. This is achieved by implementing the Vedic multiplier using Adiabatic Logic ad Vedic sutra. Vedic mathematics suggests many sutras, where Urdhava Tiryakbhyam is dedicated for multiplication of N*N numbers. In the proposed work partial sum and products are obtained in single iterative step. ac power supply is used by Adiabatic Logic instead of de power supply. In the proposed work, the design of Vedic Multiplier is done using 180nm CMOS processing technology through Cadence Virtuoso tool