A 5V only 1 Tr, 256K EEPROM with page mode erase

Abstract

Recently, several types of Rash EEPROMs have been proposed 1 ' ) 1 3 1 . These Bash EEPROMs, however, require a external high voltage supply for programming and the rrose/wntc cycling of them is one or two orders less than that of normal EEPROMs, because programming is accomplished by hot electron injection into the Boating gate. On the other hand, the memory cell of nornivl EEPROM8 which is byte erase type consists of two transistors, that is a bit select transistor and D memory transistor, and has a byte select transistor per byte. The chip sise is two to three timea larger than that of EPROM8 and Baah EEPROMs, because four parity bite per byte are required for ECC in addition to the large cell a i m This paper presents a 5V only 1 Tr. page erase type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program iuhibited by applying U program inhibiting voltage to the draina and the control gates. The number of parity bit for ECG is five per two bytes, which are controled by LB signal. LB is the lowest address input. The total number of memory cells is 88 % compared to byte erase type EEPROMs and the chip siae has been substantially reduced. The device has fast two byte serial I C E O ~ I mode.