An accurate interconnection length estimation for computer logic

Abstract

Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor /spl delta//spl ap/2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.