A 1.25Gbps Programmable FPGA I/O Buffer with Multi-Standard Support

Abstract

In this paper, a field programmable gate array (FPGA) I/O buffer developed to support 1.25 gigabits-per-second differential source-synchronous standards is presented. The I/O buffer provides the compatibility of 38 high-speed I/O standards, features wide supply voltage range, programmable drive strength and controlled impedance driver. To enhance the performance and drive capacity of low voltage standards, an auxiliary supply is introduced into the I/O buffer. The proposed I/O buffer has been fabricated and integrated in an SRAM-based FPGA with commercial 65nm CMOS technology.