ISA configurability of an FPGA test-processor used for board-level interconnection testing

Abstract

This paper presents a study of FPGA test-processor configurability at the instruction set architecture (ISA) level used for board-level interconnection testing. The ISA configurability is used as adaptation mechanism to the test requirements, the FPGA properties, and the devices under test (DUTs). The aim is to show the advantages and limitations of processor configurability at this level, and demonstrate them in the FPGA based test system (FBTS) developed for board-level interconnection testing. The paper presents the test-processor's concept, adaptation aspects, and architecture, followed by experimental results performed with different processor configurations. Results show the advantages of having a configurable test-processor in terms of performance and FPGA resource utilization.