Q. Huang, E. M. Sankara Narayanan, K. Kwan, G. Amaratunga, W. Milne
{"title":"A novel heavily doped drift - auxiliary cathode lateral insulated gate transistor structure","authors":"Q. Huang, E. M. Sankara Narayanan, K. Kwan, G. Amaratunga, W. Milne","doi":"10.1109/ISPSD.1990.991068","DOIUrl":null,"url":null,"abstract":"A novel CMOS-compatible, heavily doped drift auxiliary cathode lateral insulated gate transistor (HDD-ACLIGT) structure is analyzed using two-dimensional device simulation techniques. Simulation results indicate that low on-resistance and a fast turn-off time of less than 50 ns can be achieved by incorporating an additional n+ region which is self-aligned to the gate between the p+ auxiliary cathode and the p well, together with an extended p buried layer in an anode-shorted modified lateral insulated gate transistor (MLIGT) structure. The on-state and its transient performance are analyzed in detail. The on-state performances of the HDD-ACLIGT and the MLIGT are compared and discussed. The results indicate that the HDD-ACLIGT structure is well suited for HVICs. The device is also well suited for integration with self-aligned digital CMOS.","PeriodicalId":162198,"journal":{"name":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1990.991068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A novel CMOS-compatible, heavily doped drift auxiliary cathode lateral insulated gate transistor (HDD-ACLIGT) structure is analyzed using two-dimensional device simulation techniques. Simulation results indicate that low on-resistance and a fast turn-off time of less than 50 ns can be achieved by incorporating an additional n+ region which is self-aligned to the gate between the p+ auxiliary cathode and the p well, together with an extended p buried layer in an anode-shorted modified lateral insulated gate transistor (MLIGT) structure. The on-state and its transient performance are analyzed in detail. The on-state performances of the HDD-ACLIGT and the MLIGT are compared and discussed. The results indicate that the HDD-ACLIGT structure is well suited for HVICs. The device is also well suited for integration with self-aligned digital CMOS.