{"title":"A Ku-band 6-bit phase shifter in 0.35-μm SiGe BiCMOS technology","authors":"X. Han, Kaixue Ma, Shouxian Mou, F. Meng","doi":"10.1109/EDAPS.2017.8276987","DOIUrl":null,"url":null,"abstract":"This paper presents a 6-bit digital phase shifter designed at Ku-band for electronic beam steering of satellite based phased array antenna systems, which is implemented in a commercial 0.35-μm SiGe BiCMOS technology. The 6-bit phase shifter utilizes embedded switched filter structure with n-MOS transistors as switches. Four different phase shifter topologies are adopted to achieve the desired insertion phases with accurate phase shifting control, low insertion loss and small inter-state amplitude errors. The simulated performance of all 64 states of the phase shifter demonstrates an insertion loss of 11±2.7 dB and a RMS phase error of <5°, and P1dB of better than 16 dBm. The input/output return losses are better than −8 dB over the 14–18 GHz frequency range respectively. And the chip size of this prototype is only 1.4×0.93 mm2 excluding PADs.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2017.8276987","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a 6-bit digital phase shifter designed at Ku-band for electronic beam steering of satellite based phased array antenna systems, which is implemented in a commercial 0.35-μm SiGe BiCMOS technology. The 6-bit phase shifter utilizes embedded switched filter structure with n-MOS transistors as switches. Four different phase shifter topologies are adopted to achieve the desired insertion phases with accurate phase shifting control, low insertion loss and small inter-state amplitude errors. The simulated performance of all 64 states of the phase shifter demonstrates an insertion loss of 11±2.7 dB and a RMS phase error of <5°, and P1dB of better than 16 dBm. The input/output return losses are better than −8 dB over the 14–18 GHz frequency range respectively. And the chip size of this prototype is only 1.4×0.93 mm2 excluding PADs.