{"title":"Selectable Length Partial Scan: A Method to Reduce Vector Length","authors":"Sean P. Morley, R. Marlett","doi":"10.1109/TEST.1991.519698","DOIUrl":null,"url":null,"abstract":"Partial scan is an increasingly popular testability solution, but the test program length it requires is a growing concern. This paper proposes a selectable length sican implementation that can dramatically reduce the shifting requirements. Equations are developed, based on a statistical approach, to predict the reduction. A practical methodology to implement the technique is presented. 'The easily calculated estimate is shown to be in excellent agreement with actual results. This technique uses the sizme number of test pins as other scan methods, compliles with industry standards, is broadly applicable, and has provided greater than 70% test program length reduction on .a variety of commercially designed circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"71","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991, Proceedings. International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1991.519698","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 71
Abstract
Partial scan is an increasingly popular testability solution, but the test program length it requires is a growing concern. This paper proposes a selectable length sican implementation that can dramatically reduce the shifting requirements. Equations are developed, based on a statistical approach, to predict the reduction. A practical methodology to implement the technique is presented. 'The easily calculated estimate is shown to be in excellent agreement with actual results. This technique uses the sizme number of test pins as other scan methods, compliles with industry standards, is broadly applicable, and has provided greater than 70% test program length reduction on .a variety of commercially designed circuits.