A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits

Abstract

We present an analytical method to perform VLSI standard cell placement. We have developed a placement engine based on analytical methods that makes use of non-linear programming. At first we cluster a net list to reduce the number of cells. In the second step we perform quadratic optimization on the reduced net list. Finally we use conjugate gradient method for solving non-linear equations for the problem. The framework of our tool, Kapees2, is scalable and generates high quality results. We obtain results for IBM version 2 benchmarks which show promising results. Our placer outperforms Capo, Amoeba, NTUPlace3 and feng shui by 7%, 12%, 2% and 1%, respectively.