Area-efficient implementation of a fast square root algorithm

Abstract

An area-efficient implementation of a fast-converging square-root algorithm is presented. The design of special arithmetic operations differs in many ways from the traditional tasks that digital designers are used to, and the role of parameterizability and mapping of mathematical algorithms onto digital hardware is discussed. Certain real-world applications requiring the use of the square-root operator are presented, and it is argued that implementing special arithmetic operations directly in hardware offers significant speed advantages over the conventional approach of implementing them in software. The mathematical algorithm of the square-root operator is described, and its applicability to an implementation in digital logic is presented. It also is shown that the square-root operator can be efficiently implemented without the need to resort to multiplications or divisions, which is advantageous in terms of both area and timing.