RACER: a reconfigurable constraint-length 14 Viterbi decoder

Abstract

This paper describes the architecture and implementation of a constraint-length 14 Viterbi decoder that achieves a decoding rate of 41 Kbits/s. The system uses 36 Xilinx XC4010 FPGAs with seven processor cards and a custom backplane to implement a multi-ring general cascade Viterbi decoder architecture. The paper also shows how to achieve decoding rates of 1 Mbit/s using current FPGA technology. Comparisons are made to JPL's big Viterbi decoder, which uses custom ASICs.