Modeling VHDL specifications as consistent EFSMs

Abstract

The dramatic increase in the complexity of digital systems has led to the use of formal description languages such as VHDL. This paper presents the preliminary results on properties of VHDL specifications that allow for automatic test generation without the exponential growth. In general, VHDL specifications can be modeled as extended finite machines (EFSMs). A class of EFSMs, called consistent EFSMs, allows for the finite state machines (FSM) based test generation techniques to be directly applied to VHDL specifications. An algorithm to identify the consistent EFMSs is introduced.