A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS

Abstract

A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13mum digital CMOS process. The gain and matching errors of the analog circuitry are compensated by a digital calibration scheme that allows the usage of a low-gain op-amp. A low power consumption has been reached by introducing a charge compensation scheme