One new architecture of fractional frequency synthesizer

M. Stork
{"title":"One new architecture of fractional frequency synthesizer","authors":"M. Stork","doi":"10.1109/RADIOELEK.2008.4542709","DOIUrl":null,"url":null,"abstract":"This paper describes a new architecture of a digital fractional frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other method e.g. SigmaDelta fractional-N frequency synthesizers or direct digital synthesis. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable Large Scale Integration (or in-system programmable Large Scale Integration). On the other hand, this synthesizer has a disadvantage in low output frequency, but this can be overcome by using this synthesizer together with phase locked loop.","PeriodicalId":162482,"journal":{"name":"2008 18th International Conference Radioelektronika","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 18th International Conference Radioelektronika","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADIOELEK.2008.4542709","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper describes a new architecture of a digital fractional frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other method e.g. SigmaDelta fractional-N frequency synthesizers or direct digital synthesis. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable Large Scale Integration (or in-system programmable Large Scale Integration). On the other hand, this synthesizer has a disadvantage in low output frequency, but this can be overcome by using this synthesizer together with phase locked loop.
分数频率合成器的一种新结构
本文介绍了一种基于发生器、计数器和寄存器的数字分数频率合成器的新结构。这里描述的技术比其他方法简单得多,例如SigmaDelta分数n频率合成器或直接数字合成器。所提出的合成器最适合设计VLSI架构或可编程大规模集成(或系统内可编程大规模集成)。另一方面,该合成器的缺点是输出频率低,但这可以通过与锁相环一起使用来克服。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信