One new architecture of fractional frequency synthesizer

Abstract

This paper describes a new architecture of a digital fractional frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other method e.g. SigmaDelta fractional-N frequency synthesizers or direct digital synthesis. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable Large Scale Integration (or in-system programmable Large Scale Integration). On the other hand, this synthesizer has a disadvantage in low output frequency, but this can be overcome by using this synthesizer together with phase locked loop.