Instruction Cache Design for Energy-Aware Embedded Processors by Using Backward Branch Information

Abstract

Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful embedded processors. Unfortunately, as the computing power of a processor increases, energy consumption in the processor dramatically increases. For this reason, energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in a embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Analysis results show that the proposed cache reduces the energy consumption by 20% on the average, compared to the traditional cache.