Hot Carrier Degradation in Cryo-CMOS

W. Chakraborty, Uma Sharma, S. Datta, S. Mahapatra
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引用次数: 4

Abstract

28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (VG/VD) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔVT) into interface trap generation due to pure HCD (ΔVIT-HC), Bias Temperature Instability (BTI, ΔVIT-BT), and electron/hole trapping (ΔVET/ΔVHT) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.
Cryo-CMOS中的热载流子降解
分析了28nm Gate First High-K Metal Gate (GF-HKMG)技术在不同栅极/漏极(VG/VD)偏置和温度(T: 300K至77K)下的热载流子降解(HCD)。使用紧凑的模型将测量的阈值电压位移(ΔVT)划分为由于纯HCD (ΔVIT-HC),偏置温度不稳定性(BTI, ΔVIT-BT)和电子/空穴捕获(ΔVET/ΔVHT)子组件而产生的界面陷阱。虽然纯HCD在cro - cmos操作下占主导地位,但对于Si NMOS和SiGe PMOS fet, T依赖性有所不同。最后,分析了对环形振荡器(RO: Ring Oscillator)工作的影响。
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