A comparison of 10 GHz frequency dividers in bulk and SOI 0.13 /spl mu/m CMOS technologies

A. Engelstein, J. Fournier, V. Knopik, C. Raynaud
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Abstract

The goal of this paper is to focus on the advantages of SOI technologies for high speed digital circuits for RF application, through the study of the consumption of 10 GHz frequency dividers. Dynamic and static structures are implemented in bulk and SOI CMOS 0.13 /spl mu/m technologies, and the measured consumptions are compared. As the capacitance of the drain-source diffusions and interconnections are reduced in SOI because of the BOX, dynamic consumption reductions of 20 % and 25 % are measured between bulk and SOI technologies, respectively for the dynamic and static structure.
10 GHz分频器与SOI 0.13 /spl mu/m CMOS技术的比较
本文的目标是通过对10ghz分频器的功耗研究,重点介绍SOI技术在高速射频数字电路中的优势。采用批量和SOI CMOS 0.13 /spl mu/m技术实现了动态和静态结构,并对测量的功耗进行了比较。由于BOX在SOI中降低了漏源扩散和互连的电容,因此在散装和SOI技术之间,动态和静态结构的动态功耗分别降低了20%和25%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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