T. Enomoto, A. Hirobe, T. Satoh, M. Fujii, N. Yoshida, S. Wada, M. Tokushima
{"title":"A high-speed, low-power 16-bit 0.25 /spl mu/m GaAs binary look-ahead carry (BLC) adder based on NOR gates for wireless video communication","authors":"T. Enomoto, A. Hirobe, T. Satoh, M. Fujii, N. Yoshida, S. Wada, M. Tokushima","doi":"10.1109/MTTTWA.1999.755145","DOIUrl":null,"url":null,"abstract":"A fast, low-power, and small 16-bit adder was fabricated using 0.25-/spl mu/m GaAs HJFET technology for future wireless video communication. This adder, which uses negative logic binary look-ahead carry (BLC) structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm/sup 2/ and there are about 1,230 FETs.","PeriodicalId":261988,"journal":{"name":"1999 IEEE MTT-S International Topical Symposium on Technologies for Wireless Applications (Cat. No. 99TH8390)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE MTT-S International Topical Symposium on Technologies for Wireless Applications (Cat. No. 99TH8390)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTTTWA.1999.755145","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A fast, low-power, and small 16-bit adder was fabricated using 0.25-/spl mu/m GaAs HJFET technology for future wireless video communication. This adder, which uses negative logic binary look-ahead carry (BLC) structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm/sup 2/ and there are about 1,230 FETs.