On-chip analog response extraction with 1-bit /spl Sigma/-/spl Delta/ modulators

Hao-Chiao Hong, Jiun-Lang Huang, K. Cheng, Cheng-Wen Wu
{"title":"On-chip analog response extraction with 1-bit /spl Sigma/-/spl Delta/ modulators","authors":"Hao-Chiao Hong, Jiun-Lang Huang, K. Cheng, Cheng-Wen Wu","doi":"10.1109/ATS.2002.1181684","DOIUrl":null,"url":null,"abstract":"Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2002.1181684","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.
片上模拟响应提取与1位/spl Sigma/-/spl Delta/调制器
由于对工艺变化具有相对的鲁棒性,/spl Sigma/-/spl Delta/调制技术特别适用于VLSI实现。在本文中,我们建议采用1位/spl Sigma/-/spl Delta/调制ADC(模数转换器)作为片上模拟响应提取器,用于模拟/混合信号BIST(内置自检)应用。为了验证这个想法,已经设计并制造了一个带有所提出的BIST电路的原型芯片。验证了BIST电路的性能(动态范围高达87 dB),并给出了被测电路(CUT)的测量结果,该电路是一个二阶低通滤波器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信