Extending EDA environment from design to test

Abstract

For first silicon, detection of systematic defects, timing failure and other errors is an extremely time-pressured task because detection and debugging of such failures determines how fast a product can go into mass production. In this paper we describe a new method for this purpose using an event tester. This method allows testing in the same environment as used for the original simulation in which the chip was designed. The method uses original design simulation data directly from the Verilog/VHDL simulation in the VCD format and thus, eliminates test program generation and test vector translation processes into WGL/STIL or ATE formats. It essentially extends the EDA design environment to the physical testing of an IC.