Yield modeling and optimization of large redundant RAMs

Abstract

Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global redundancy schemes for TRAM.<>